1. Field
Various features relate to physically unclonable functions (PUFs), and in particular to PUFs based on the programming voltages of an array of magnetoresistive random-access memory (MRAM) cells.
2. Background
An on-chip PUF is a chip-unique challenge-response mechanism exploiting manufacturing process variations inside integrated circuits (ICs). When a physical stimulus (i.e., challenge) is applied to the PUF, the PUF generates a response in an unpredictable but repeatable way due to the complex interaction of the stimulus with the physical microstructure of the device employing the PUF. This exact microstructure depends on physical factors introduced during manufacture of the device employing the PUF, which are unpredictable. The PUF's “unclonability” means that each device employing the PUF has a unique and unpredictable way of mapping challenges to responses, even if one device is manufactured with the same process as another seemingly identical device. Thus, it is practically infeasible to construct a PUF with the same challenge—response behavior as another device's PUF because exact control over the manufacturing process is infeasible.
MRAM is a non-volatile random-access memory that, unlike conventional RAM, stores data not as electric charge but instead as electron spin within magnetic storage elements. FIG. 1 illustrates a simplified schematic diagram of the magnetic storage elements 100 that form part of an MRAM circuit cell found in the prior art. Referring to FIG. 1, the magnetic storage elements 100 include a first ferromagnetic layer 102 and a second ferromagnetic layer 104 that are separated by a very thin insulating layer 106. The magnetic layers 102, 104 each hold a magnetic field with a specific direction of polarity. The second magnetic layer 104, also known as a “pinned reference layer,” may be a permanent magnet with a magnetic polarity that is fixed (as shown by the solid arrow). The magnetic polarity of the first magnetic layer 102, also known as a “free layer,” is not fixed and may be changed by an external magnetic field (not shown). For example, as indicated by the dashed arrows the magnetic polarity of the first magnetic layer 102 may be oriented either parallel or antiparallel to the magnetic polarity of the second magnetic layer 104. The thin insulating layer 106 is made of a very thin insulating material that separates the two magnetic layers 102, 104. The thin insulating layer 106 is also known as a “tunneling layer” in that it is so thin that electrons can flow (i.e., tunnel) through its thickness between the two magnetic layers 102, 104 despite the tunneling layer 106 being an insulator.
If the polarity of the first magnetic layer 102 is oriented such that it is parallel to the second magnetic layer 104, then the resistance between the layers 102, 104 is relatively low (i.e., low resistance state). Such a state may be considered to represent a data bit “0” state (logical state “0”). By contrast, if the polarity of the first magnetic layer 102 is oriented such that it is anti-parallel to the second magnetic layer 104, then the resistance between the layers 102, 104 is relatively high (i.e., high resistance state). Such a state may be considered to represent a data bit “1” state (logical state “1”).
FIG. 2 illustrates an MRAM circuit cell 200 found in the prior art. A transistor 202 coupled to the magnetic storage elements 100 controls the flow of current through the storage elements 100. If the transistor 202 is turned ON current flows through the magnetic storage elements 100 as indicated by the downward dashed arrow. Depending on the resistance state (i.e., logical state) of the magnetic storage elements 100, the current flow will either be relatively high or relatively low. Thus, data may be read from the MRAM circuit cell 200 by turning on the transistor 202 and measuring the current flow through the read line 204. A relatively high current flow means the resistance state of the magnetic storage elements is low and thus a “0” bit is stored. A relatively low current flow means the resistance state of the magnetic storage elements is high and thus a “1” bit is stored.
Referring to FIGS. 1 and 2, data may be written to the cell 200 (i.e., the logical state may be changed) by changing the polarity of the first magnetic layer 102. A programming signal 206 (e.g., a write-line signal) supplies a voltage/current to the magnetic storage elements 100 that causes the polarity of the first magnetic layer 102 to change direction, and thus the data bit stored changes from a “0” to a “1” or a “1” to a “0.” The programming signal's 206 voltage (herein also referred to as “programming signal voltage VPS”) must exceed the transition voltage VT of the magnetic storage elements 100 in order for the data bit transition to occur.
There exists a need for methods and apparatuses that implement PUFs based on MRAM cells. Such MRAM based PUFs may provide a secure means to uniquely identify electronic devices, such as integrated circuits, and/or provide secure cryptographic keys for cryptographic security algorithms.